Memory circuits, systems, and methods for providing bit line equalization voltages
US8279686B2 · kind B2 · utility
5Cited by
13References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Dec 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.