Single supply sub VDD bit-line precharge SRAM and method for level shifting
US8279687B2 · kind B2 · utility
28Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | May 13, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Mar 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.