Signaling with superimposed differential-mode and common-mode signals
US8279976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Mar 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0262
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.