System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
US8281272B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2011 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Oct 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster to generate a core layout cell; and storing the generated core layout cell in non-transitory storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.