Method and apparatus for versatile controllability and observability in prototype system
US8281280B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 11, 2011 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Feb 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.