Method to form a semiconductor device having gate dielectric layers of varying thickness
US8283222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2011 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.