MOS structures that exhibit lower contact resistance and methods for fabricating the same
US8283233B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2011 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Jun 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.