Method of manufacturing wafer level package
US8283251B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2011 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.