Multi-die integrated circuit device and method
US8283771B2 · kind B2 · utility
6Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Mar 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.