Thermally balanced via
US8283778B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2007 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.