Delay-locked loop and electronic device including the same
US8283958B2 · kind B2 · utility
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1References
16Claims
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Key dates
| Filing date | Feb 23, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Jun 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.