Refresh control circuit and method for semiconductor memory device
US8284615B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Mar 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.