Patent · US Active

Techniques for processor/memory co-exploration at multiple abstraction levels

US8285535B2 · kind B2 · utility

1Cited by

25References

16Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Gunnar Braun · Aachen, DE
Olaf Zorres · Aachen, DE
Achim Nohl · Aachen, DE
Andreas Hoffmann · North Bend, US

Key dates

Filing date	Aug 30, 2010
Grant date	Oct 9, 2012
Priority date	—
Expiry date	Aug 30, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2117/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.