Patent · US Active

Flattened butterfly processor interconnect network

US8285789B2 · kind B2 · utility

10Cited by

0References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Dennis C. Abts · Eau Claire, US
John Kim · Glenview, US
William J. Dally · Stanford, US

Key dates

Filing date	Aug 20, 2008
Grant date	Oct 9, 2012
Priority date	—
Expiry date	Dec 11, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/17375
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.