Input/output device including a mechanism for accelerated error handling in multiple processor and multi-function systems
US8286027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Dec 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0766
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.