On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability
US8286042B2 · kind B2 · utility
12Cited by
9References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Mar 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318385
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.