Inventor · Plainsboro, NJ, US

Srivaths Ravi

13Patents
7h-index
23Co-inventors
62Inventor score

Filing activity: Mar 15, 2002 → Dec 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7134100B2 Method and apparatus for efficient register-transfer level (RTL) power estimation Physics 36 Expired
US8205125B2 Enhanced control in scan tests of integrated circuits with partitioned scan chains Physics 30 Active
US7278123B2 System-level test architecture for delivery of compressed tests Physics 29 Expired
US8286042B2 On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability Physics 12 Active
US8671329B2 Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes Physics 11 Active
US8438344B2 Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes Physics 9 Active
US7173906B2 Flexible crossbar switching fabric Electricity 8 Expired
US7529669B2 Voice-based multimodal speaker authentication using adaptive training and applications thereof Physics 6 Active
US7260809B2 Power estimation employing cycle-accurate functional descriptions Physics 4 Expired
US8839063B2 Circuits and methods for dynamic allocation of scan test resources Physics 2 Active
US11333707B2 Testing of integrated circuits during at-speed mode of operation Physics 2 Active
US8856601B2 Scan compression architecture with bypassable scan chains for low test mode power Physics 2 Active
US8527821B2 Hybrid test compression architecture using multiple codecs for low pin count and high compression devices Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.