3-dimensional device design layout
US8286114B2 · kind B2 · utility
11Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2007 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Nov 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.