Systematic method for variable layout shrink
US8286119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.