Method for fabricating a tunneling field-effect transistor
US8288238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Oct 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/021
Abstract
The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.