Inventor · Beijing, CN

Runsheng Wang

14Patents

3h-index

26Co-inventors

52Inventor score

Filing activity: Sep 25, 2010 → Mar 20, 2017

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9018968B2	Method for testing density and location of gate dielectric layer trap of semiconductor device	Electricity	15	Active
US8513067B2	Fabrication method for surrounding gate silicon nanowire transistor with air as spacers	Electricity	9	Active
US8564031B2	High voltage-resistant lateral double-diffused transistor based on nanowire device	Electricity	8	Active
US8288238B2	Method for fabricating a tunneling field-effect transistor	Electricity	3	Active
US9478641B2	Method for fabricating FinFET with separated double gates on bulk silicon	Electricity	2	Active
US8563370B2	Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls	Electricity	2	Active
US8901644B2	Field effect transistor with a vertical channel and fabrication method thereof	Electricity	2	Active
US8372752B1	Method for fabricating ultra-fine nanowire	Performing Operations; Transporting	1	Active
US9034702B2	Method for fabricating silicon nanowire field effect transistor based on wet etching	Electricity	1	Active
US10621386B1	Method of bias temperature instability calculation and prediction for MOSFET and FinFET	Physics	1	Active
US9099500B2	Programmable array of silicon nanowire field effect transistor and method for fabricating the same	Electricity	0	Active
US8866507B2	Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact	Electricity	0	Active
US8722312B2	Method for fabricating semiconductor nano circular ring	Performing Operations; Transporting	0	Active
US8592276B2	Fabrication method of vertical silicon nanowire field effect transistor	Performing Operations; Transporting	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.