Methods for avoiding parasitic capacitance in an integrated circuit package
US8288269B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/111
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.