Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US8288869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.