Integrated circuit having receiver jitter tolerance (“JTOL”) measurement
US8289032B2 · kind B2 · utility
14Cited by
6References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2008 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Feb 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.