Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter models
US8290761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Apr 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for rapidly modeling and simulating intra-die variations in an integrated circuit are disclosed. In one embodiment, each logic gate in an integrated circuit has a characteristic to be simulated, where the characteristic of the gate is a function of one or more parameters having intra-die variations. For each parameter, a model of intra-die variation of the parameter is generated such that a number of random variables in the model is compressed to a reduced number (r) of random variables based on a spatial correlation of the intra-die variation of the parameter. Then, using a Quasi Monte Carlo (QMC) technique, the integrated circuit is simulated based on the model of the intra-die variation of each of the one or more parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.