On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations

US8291357B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Serafino Bueti · Waterbury, US
• Adam J. Courchesne · Granby, US
• Kenneth J. Goodnow · South Burlington, US
• Todd E. Leonard · Williston, US
• Peter A. Sandon · South Burlington, US
• Peter A. Twombly · Shelburne, US
• Charles S. Woodruff · Vergennes, US

Key dates

• Filing date: Oct 9, 2007
• Grant date: Oct 16, 2012
• Expiry date: Apr 25, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19043
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.