Scheduling optimization of aliased pointers for implementation on programmable chips
US8291396B1 · kind B1 · utility
6Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various high-level languages are used to specify hardware designs on programmable chips. The high-level language programs include pointer operations that may have same iteration and future iteration dependencies. Single loop iteration pointer dependencies are considered when memory accesses are assigned to clock cycles. Multiple loop iteration pointer dependencies are considered when determining how often new data can be entered into the generated hardware pipeline without causing memory corruption. A buffer can be used to forward data from a memory write to a future read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.