Dependent instruction thread scheduling
US8291431B2 · kind B2 · utility
4Cited by
6References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A thread scheduler includes context units for managing the execution of threads where each context unit includes a load reference counter for maintaining a counter value indicative of a difference between a number of data requests and a number of data returns associated with the particular context unit. A context controller of the thread context unit is configured to refrain from forwarding an instruction of a thread when the counter value is nonzero and the instruction includes a data dependency indicator indicating the instruction requires data returned by a previous instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.