Hybrid bonding techniques for multi-layer semiconductor stacks
US8293578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Oct 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.