Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers
US8293598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2009 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Jun 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.