Method of manufacturing semiconductor devices
US8293642B2 · kind B2 · utility
465Cited by
0References
18Claims
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Assignee
Inventor
Key dates
| Filing date | Mar 7, 2011 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Mar 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor devices includes forming a dielectric interlayer over a semiconductor substrate, wherein a wet etch rate (WER) is faster in an upper part of the dielectric interlayer than in a lower part of the dielectric interlayer, forming trenches in the dielectric interlayer, performing a cleaning process to make a width of an opening portion in an upper part of each of the trenches wider than a width of an opening portion in lower part of the trench, and filling the trenches with a metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.