Stressed magnetoresistive tamper detection devices
US8294577B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2008 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Aug 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1695
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tamper sensing system mounted with respect to a protected structure so as to have corresponding stress changes occur therein in response to selected kinds of tamperings with said protected structure comprising a first pair of stress affected magnetoresistive memory devices each capable of having a magnetic material layer therein established in a selected one of a pair of alternative magnetization states if in a first kind of stress condition and of being established in a single magnetization state if in an alternative second kind of stress condition, and the magnetic material layer in each having a magnetization in a first direction in one of the pair of alternative magnetization states and in a second direction in that remaining one of the pair of magnetization states. A first magnetizing electrical conductor extends adjacent to each of the first pair of stress affected magnetoresistive memory devices to establish said magnetic material layer in that one of said pair of alternative magnetization states thereof so as to have its said corresponding magnetization be oppositely directed with respect to said magnetization of that other. The first pair of stress affected magnetoresist…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.