Dual port memory with write assist
US8295099B1 · kind B1 · utility
19Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e.g., Vdd) is coupled to the bitlines (e.g., BL-A, BLc-A) of the first port during the WRITE assist pulse, and a low voltage value (e.g., zero) is written to the memory cell through the second port (e.g., BL-B, BLc-B) during the clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.