Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system
US8295419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.