Microprocessor with selectively available random number generator based on self-test result
US8296345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2006 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Mar 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The microprocessor also includes a self-test unit that performs the self-test in response to a reset. The microprocessor also includes an instruction translator that translates instructions of the instruction set architecture, including instructions related exclusively to operation of the random number generator. The microprocessor generates a fault defined by the instruction set architecture in response to execution of one of the plurality of instructions related exclusively to operation of the random number generator if the self-test unit previously determined the random number generator is not operating properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.