Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system
US8296524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Apr 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.