Patent · US Active

Secure processor arrangement having shared memory

US8296581B2 · kind B2 · utility

5Cited by

4References

41Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Gerard David Jennings · Peising, DE
Eckhard Delfs · Nuremberg, DE

Key dates

Filing date	Feb 5, 2007
Grant date	Oct 23, 2012
Priority date	—
Expiry date	Jul 1, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/71
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.