Integrated circuit comprising error correction logic, and a method of error correction
US8296621B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Nov 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/64315
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises forward error correction (FEC) decoder logic being coupled to memory and arranged to receive data, comprising application data, from a host application process. The FEC decoder logic performs error detection upon the received data. Logic is further arranged to transmit error free application data back to the host application process prior to performing error correction; and store in memory only application data in which errors are detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.