Handling two-dimensional constraints in integrated circuit layout
US8296706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Dec 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.