Method of constraint-hierarchy-driven IC placement
US8296708B1 · kind B1 · utility
2Cited by
5References
18Claims
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Key dates
| Filing date | Jan 13, 2012 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a computer-implemented method to generate a placement for a plurality of device modules within an analog integrated circuit (IC) subject to a set of constraints. By building a constraint hierarchy tree according to the constraints, conflicts of constraints can be identified and resolved. Furthermore, placements can be generated based on the hierarchy tree through a bottom-to-top dimension optimization process and a top-down wire length optimization process. Furthermore, a graphical user interface can be used to display the tree, and the user can edit the tree visually and interactively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.