Packaged electronic devices having die attach regions with selective thin dielectric layer
US8298874B2 · kind B2 · utility
2Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2012 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jun 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.