Method for fabrication of a semiconductor device and structure
US8298875B1 · kind B1 · utility
68Cited by
186References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 6, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Mar 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.