Shielding for high-voltage semiconductor-on-insulator devices
US8299561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.