Isolation structure and device structure including the same
US8299562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.