Alignment of wafers for 3D integration
US8299584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of aligning substrates, e.g., semiconductor wafers, is provided in which a first substrate can be at least coarsely aligned atop a second substrate. Each substrate can have a pattern thereon, wherein the pattern of the first substrate can be aligned with a window of the first substrate. A return signal can be returned from simultaneously illuminating the patterns of the first and second substrates through the window in the first substrate. The return signal can be compared to at least one stored signal to determine relative misalignment between the first and second substrates. A position of at least one of the first and second substrates can be altered relative to a position of the other of the first and second substrates to address the misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.