Borderless interconnect line structure self-aligned to upper and lower level contact vias
US8299625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.