Method and circuit for calibrating data capture in a memory controller
US8300464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.