Memory controller with loopback test interface
US8301941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Nov 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31716
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.