Low-density parity-check code based error correction for memory device
US8301963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2007 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2129
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An accumulative repeat encoder facilitates encoding data written to memory, such that parity data is generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data is stored in memory. During a read operation, a decoder component utilizes the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component is iterative and provides one or more decoding results based on probabilities that symbols or bits comprising the data have correct values. The decoder component analyzes a decoding result and references a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result is determined to represent the original data and is provided as an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.