Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders
US8301979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Feb 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the first decoder. Probability values such as logarithmic likelihood ratio (LLR) values may be clipped in the second decoder. This approach can overcome trapping sets while exhibiting low complexity and high performance. Further, it can be implemented on existing decoders such as those used in current memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.